Integrated circuit design planning is typically accomplished utilizing a variety of design tools. These tools enhance the creation of a workable layout so that integrated circuits may be fabricated using semiconductor fabrication equipment and techniques. One type of integrated circuit which requires a significant amount of labor in the development of a functional layout is the Application Specific Integrated Circuit or ASIC. ASICs are chips containing an array of hardware logic devices configured by a system designer to execute a certain function. One problem with the creation of such complex ASICs is the ability of the integrated circuit designer to determine the optimal location of components on the die for accomplishing desired performance goals.
The process of integrated circuit design, including ASIC design, usually consists of the design and logical layout of an integrated circuit followed by physical design, or the creation and proper placement of a routable circuit. Creation generally consists of the positioning of the various components of a circuit design according to the desired performance goals within a confined area of a die layout, usually referred to as a “floor-plan”. For example, the circuit may be created from register transfer level (RTL) code and positioned on they die to meet the objectives of the design RTL code. A floor-plan is typically created by a design tool known as a planner. The floor-planning stage generally consists of defining the size of the integrated circuit, developing I/O pad locations, and creating groups and regions.
Placement generally consists of the placing cells in desired locations. Placement may be conducted by a design tool commonly referred to as a “placer”. Properly placed designs are those that meet the design rules of the target silicon technology and are routable by a detailed router. Typical placement methods for achieving this goal include generating one or more initial placements and modifying the placement or placements using optimization methodologies such as simulated annealing, genetic algorithms (i.e. simulated evolution), and force directed placement. Each of these techniques involves iterative applications of the respective algorithms to arrive at an estimate of the optimal arrangement of the cells. Errors in this stage often manifest themselves as problems such as timing violations, placement congestion, or routing congestion later in the physical design process. An incorrect placement of certain fixed cells such as mega cells or I/O cells can spatially constrain placement of non-fixed cells such as logic cells or flip-flop cells. This may result in the placement of non-fixed cells into sub-optimal locations, reducing performance capabilities and functionality.
Physical design has been accomplished if a circuit achieves the performance goals of a design. If a design fails to meet performance goals, such as realistic timing objectives, a timing closure problem arises. Timing closure is generally known in the art as the breakdown in the predictable timing relationship between logical and physical design. A physical designer must often resolve timing closure by utilizing various optimization tools and manually adjusting the layout until timing issues may be resolved. Timing closure is especially problematic for ASIC performance oriented designs because circuit delays in the deep submicron (DSM) arena are dominated by net delays, and influenced primarily by cell placement. Further, traditional methods for estimating interconnect delay during physical design, such as fan-out based wireload modeling, are highly inaccurate at DSM levels, creating timing unpredictability between post design and post layout results.
When physical design tools cannot automatically resolve timing closure failure on a design, a physical designer may examine the placement generated by a design tool and recognize that the timing can be closed on the design if certain design portions are clustered in a particular location on the die. The designer may then utilize a variety of floor-planning tools to create a region for a module in the design and place the region. Typically, a physical designer must manually determine appropriate area, dimensions and placement of the region. For example, a designer must determine physical area allocable to each synthesizable module in a design, the physical location of each synthesizable module, physical locations of RAM, ROM, IP and other non-synthesizable blocks in the design and I/O pad locations. These initial design parameters are generally either rough estimates, or may be determined through detailed analysis of the design, which can often be time consuming.
Another disadvantage to known creation and placement techniques is that several iterations are usually required to obtain correct region area. Specifically, ensuring that region dimensions and placement are compatible with platform-based or standard cell ASICs may require multiple iterations through physical synthesis. It is often the case that several iterations are necessary to achieve performance goals, particularly in instances where performance goals are rigorous, or if they are subject to rigid time constraints. These iterations may be additional passes through the process by which design tools create a properly placed and routable circuit, generally referred to as physical synthesis. Multiple passes through physical synthesis are generally necessary to determine region utilization. A region's area may then be modified based on the utilization information obtained by physical synthesis. Region area modification, however, often requires a designer to reconstruct a floor-plan and repeat the process of physical synthesis until an acceptable chip is produced. As a result, the manual floor planning and cell placement optimization process requires an inordinate amount of time because the process requires manual iteration between running floor-plan tools and placement tools. Also, the time and effort required increases as design size increases, further frustrating region creation and refinement. For many designs, multiple iterations can be very resource consuming as well, making chip design undesirably expensive.
Therefore, it would be desirable to provide a method and apparatus for automatic creation and placement of a floor-plan region.